A conventional ferroelectric capacitor includes one or more ferroelectric layers sandwiched between a bottom electrode and a top electrode. The ferroelectric layer(s) may include, for example, PZT, SBT or BLT. The capacitor is covered with one or more interlayer dielectric layers, normally Tetraethyl Orthosilicate (TEOS), and connection to the top electrode is achieved by etching a window through the interlayer dielectric layer(s) and filling the window with a metal filler. The bottom electrode is mounted on a substrate, the electrical connection to the bottom electrode typically being via a metal plug through the substrate. To make the connection between the bottom electrode and the plug, a window is formed through the interlayer dielectric layer(s), through the other layers of the capacitor and into the plug. A liner is formed in this window and a metal filler is deposited in the bottom of the window to make the contact between the bottom electrode and the plug. The liner and the metal filler are etched to leave just the contact to the plug. Encapsulation layers and cover layers are added to protect the resultant capacitor.
In the production of conventional capacitors it is necessary to etch the top and bottom electrodes in separate processes, and, in each case, a hard mask is used to define the etch pattern. Thus, vertical etching, that is etching down from the top layer of the device towards the substrate is a fundamental process in the manufacture of capacitor devices, such as FeRAMs. To obtain an accurate etch, the sides of the hard mask used to define the etching process should be, as near as possible, normal to the surface being etched, both when making the mask and when using the mask to etch the main cell material of the capacitor.
During the etching processes, for example, to open the hard mask (that is, to shape the hard mask material) and to etch the actual device according to the hard mask, the top of the aperture or “cut” formed whilst etching is exposed to the etching process for longer than the bottom of the aperture. Thus, more material is removed from the top of the aperture than the bottom, resulting in the aperture tapering from top to bottom, the aperture being wider at the top than at the bottom. The angle between the substrate and the etched side of the hard mask is termed the hard mask angle.
Typically, the hard mask material is TEOS. It is difficult to obtain anything approaching a 90 degree hard mask angle when etching such a material. Furthermore, when using the mask to define the etching of the remaining layers, the mask etches further, for example during the applied RIE process, thereby accentuating the problem. Although side etching, that is etching along the mask rather than through the mask, is not extensive during these processes, TEOS is a soft material for most stages in the RIE process and thus any side etching is noticeable and significant.
In view of the foregoing problems with conventional processes and devices, a need exists for an easily applied method for producing capacitors with minimal tapering of the etch apertures, without reducing production yield or compromising performance.